N.Y. Lobachevsky State University of Nizhni Novgorod


Information Technologies Laboratory

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Hardware CIL Processor

The basic idea lying under the CIL processor implementation, is direct execution of the DSP code and of the hardware CIL code, so that the target is mix of real DSP processor and hardware CIL decoder and control unit. Such implementation is very useful for software implementation of different communication protocol in the smartphones, e.g. convolution, adaptive filtration, Viterbi decoding, software radio procedures. Communication protocols, wireless link protocols, audio codecs, video codecs must be implemented as libraries in DSP native code, that allows to have very efficient and low energy consuming library code. At the opposite side, CIL instruction decoder intended for direct execution of downloaded (from Internet) business application code. Usually applications oriented for visual processing have no need in complex optimizations, because most of work inside front-end applications made inside visual form and components, but all database processing with large data amounts made on large servers. Media information processed using DSP-optimized multimedia libraries. At the point of view of the processor software model, the programmer has two instruction sets in one processor: DSP and CIL. This scheme is similar to ARM/Thumb instruction sets available in ARM cores. Depending on desired execution mode, the processor decoder can be switched between DSP and CIL instruction sets decoding. The only complex thing in the CIL processor is decoding unit, which must function in two modes: genuine DSP and CIL interpretation mode. DSP interpretation mode is quite straightforward and may be realized using standard for simple DSPs tri-staged pipeline for instruction decoding. The native DSP set instruction decoder decodes native DSP instructions, additional CIL instruction decoder maps CIL instruction into DSP core control signals. CIL decoder operates jointly with caches for CIL meta information, which are intended for speeding up common object model operations for CIL. An example for such operation is translation of object field handler for particular class into offset from the start of the object location into the memory and appropriate access operation for current field type.

The Compiler Project team is responcible for base system software for "Hardware CIL Processor" project. See project page for more details.


© RCP, 2005